Vidya Jyothi Institute of Technology - [VJIT]

Organized by: Department of Electronics & Communication Engineering, in association with IETE ISF-VJITDuration: 01 June 2026 – 06 June 2026Venue: VLSI Laboratory (E103), Department of ECE, Vidya Jyothi Institute of Technology, Hyderabad

The Department of Electronics & Communication Engineering, Vidya Jyothi Institute of Technology (VJIT), Hyderabad, successfully organized a One-Week Faculty Development Programme (FDP) on “LTSpice for EDC & ECA Laboratory Experiments” from 01 June 2026 to 06 June 2026 in association with IETE ISF-VJIT.

The programme was designed to strengthen the knowledge and practical skills of faculty members, laboratory instructors, research scholars, and students in electronic circuit simulation using LTSpice, one of the most widely used simulation tools for analog and mixed-signal circuit design. Through expert-led lectures and intensive hands-on laboratory sessions, participants gained practical experience in simulating, analyzing, and validating Electronic Devices and Circuits (EDC) and Electronic Circuit Analysis (ECA) laboratory experiments.

The Faculty Development Programme was organized with the following objectives:

The diverse participation created an interactive learning environment that encouraged knowledge sharing and collaborative problem-solving.

Participants received extensive hands-on training in the following areas:

The six-day FDP featured a blend of theoretical discussions and practical laboratory sessions, including:

Upon successful completion of the programme, participants were able to: